1. Field of the Invention
The present invention generally relates to interface circuits and, more particularly, to an interface circuit for executing processes on the link layer and the physical layer of the serial bus interface that complies with IEEE Standard 1394.
2. Description of the Related Art
The serial bus interface that complies with IEEE Standard 1394 (hereinafter, referred to as IEEE 1394 serial bus) includes a plurality of functions constituting a hierarchy that includes the physical layer, the link layer and the transaction layer in an ascending order of abstraction. The physical layer and the link layer are often implemented as hardware.
FIG. 7 is a block diagram showing a related-art interface circuit described in xe2x80x9cIEEE Standard for a High Performance Serial Bus (IEEE Aug. 30, 1996)xe2x80x9d and xe2x80x9cP1394a Draft Standard for a High Performance Serial Bus (Supplement) (IEEE Mar. 15, 1998). Referring to FIG. 7, the related-art interface circuit includes an integrated circuit for the link layer (hereinafter, referred to as a link chip) 101 for executing processes on the link layer of the IEEE 1394 serial bus interface and an integrated circuit for the physical layer (hereinafter, referred to as a PHY chip) 102 for executing processes on the physical layer of the IEEE 1394 serial bus interface.
The PHY chip 102 includes a clock generation circuit 121 for generating a local clock SCLK for the interface circuit, an encoder circuit 122 for converting data for transmission, supplied in the form of a 4-bit parallel signal, into a serial signal, generating a strobe signal based on the converted data, and supplying the strobe signal and the converted data to a port output control circuit 123 also included in the PHY chip 102. The port output control circuit 123 controls transceiver circuits 124A and 124B also included in the PHY chip 102 to transmit an arbitration control signal or the converted data and the strobe signal combined.
The transceiver circuit 124A uses the strobe signal to drive a twisted-pair cable A (hereinafter, referred to as a TPA cable) that complies with the IEEE Standard 1394, receives data transmitted from an adjacent interface circuit via the TPA cable, transmits and receives the arbitration control signal and receives a speed code indicating a data transfer rate. The transceiver 124B uses the data for transmission to drive the twisted-pair cable B (hereinafter, referred to as a TPB cable) that complies with IEEE Standard 1394, receives the strobe signal from an adjacent interface circuit via the TPB cable, transmits and receives the arbitration control signal and transmits the speed code.
The PHY chip 102 also includes a data resync circuit 125 for synchronizing the data received by the transceiver circuits 124A and 124B via the IEEE Std 1394 cables with the clock signal generated by the clock generation circuit 121. There is also included a decoder circuit 126 that provides an interface for supplying received data processed by the data resync circuit 125 to the link chip 101 in the form of a 4-bit parallel signal.
The PHY chip 102 also includes an arbiter circuit 127 for controlling, upon receipt of an arbitration request signal (hereinafter, referred to as a LREQ signal) from the link chip 101, states of the PHY chip 102 using a built-in state machine so as to execute an arbitration process. There is also included a control circuit 128 for exchanging a control signal (hereinafter, referred to as a CTL signal), indicating the status of transmission and reception, with the link chip 101, and using built-in state machines to execute, upon receipt of a predetermined control signal (hereinafter, referred to as a LPS signal) from the link chip 101, processes such as the reset of the status of the interface circuit in accordance with the LPS signal.
IEEE Standard 1394 calls for an input withstand voltage of xe2x88x920.5-+2.8 volts in the transceiver circuits 124A and 124B. In order to secure the withstand voltage of this level, a microfabrication process of 0.3 xcexcm or greater should be used to fabricate the transceiver circuits 124A and 124B of the physical chip 102.
A description will now be given of the operation of the interface circuit according to the related art.
Data for transmission is supplied as a parallel signal from the link chip 101 to the encoder circuit 122. The encoder circuit 122 converts the supplied parallel signal into a serial signal and generates a strobe signal based on the converted signal. The port output control circuit 123 supplies the serial signal for transmission and the strobe signal to the transceiver circuits 124A and 124B. The IEEE Std 1394 cables TPA and TPB are driven by the strobe signal and the data signal, respectively, so that the data for transmission is sent to an adjacent interface circuit.
When a serial signal containing transmitted data and a strobe signal are received by the transceiver circuits 124A and 124B, the serial signal and the strobe signal are supplied to the data resync circuit 125. The data resync circuit retrieves the transmitted data and the transmitted clock signal from the serial signal and the strobe signal. The data resync circuit 125 synchronizes the transmitted data thus retrieved with the clock signal generated by the clock generation circuit 121 so as to output the synchronized data to the decoder circuit 126. The decoder circuit 126 feeds the transmitted data thus supplied to link chip 101 in the form of a 4-bit parallel signal.
In an arbitration process, the link chip 101 supplies a LREQ signal to the arbiter circuit 127. The arbiter circuit 127 controls the other components of the PHY chip 102 so that an arbitration control signal is properly exchanged with an adjacent interface circuit.
When the interface circuit is reset, the link chip 101 supplies a LPS signal to the control circuit 128 so that the control circuit 128 executes a reset process such as a port reset using the built-in state machines.
Japanese Laid-Open Patent Application No. 11-4240 and No. 6-237285 disclose the technology related to the above-described interface circuit.
Since the related-art interface circuit requires that the microfabrication process of 0.3 xcexcm or greater be used to fabricate the entirety of the physical chip 102, the benefit of cost reduction by applying the current fabrication technology (0.1-0.2 xcexcm process) to the circuits other than the transceiver circuits 124A and 124B is not readily available.
Another disadvantage of the related-art interface circuit is that a total of thirteen (=1+1+2+8+1) cables are required for the SCLK signal (requiring one cable), the LREQ signal (one cable), the CTL signal (two cables), the LPS signal (one cable) and the data (the D signal containing a total of eight bits each requiring one cable) exchanged between the link chip 101 and the encoder circuit 122, and between the link chip 101 and the decoder circuit 126. Consequently, it has been difficult to reduce the cost of fabricating the circuit as a whole.
Accordingly, an object of the present invention is to provide an interface circuit in which the aforementioned drawbacks are eliminated.
Another and more specific object of the present invention is to reduce the cost of fabricating an interface circuit by accommodating some of the circuits for executing processes on the physical layer in a link chip that includes a link layer circuit. More specifically, an arbiter circuit, composed only of a logic circuitry and having a relatively large circuit scale, and state machines, built in a control circuit, are accommodated in the link chip in the form of a control signal generation circuit. The other portions of the physical layer circuit remains in the second chip. A higher degree of integration of the first chip using the current microfabrication technology results in a higher degree of integration of many of the circuitry for executing processes on the physical layer. The invention also has an object of reducing the number of cables between the link chip and the PHY chip so as to reduce the cost of the interface circuit.
The aforementioned objects can be achieved by an interface circuit for executing processes on a link layer and a physical layer of an interface that complies with IEEE Standard 1394, comprising: a first chip having a link layer circuit for executing processes on the link layer and a first control circuit for executing state transitions of the processes on the physical layer; and a second chip having a physical layer circuit for executing processes on the physical layer based on the state transitions executed by the first control circuit.
The first control circuit may generate a control signal corresponding to a state of the processes on the physical layer, and the second chip may include a second control circuit for controlling the physical layer circuit in accordance with a control signal.
The second chip may be provided with physical layer circuits for an equal number of ports, second control circuits for the equal number of ports, and a port control circuit for connecting with the first chip the physical layer circuit and the second control circuit corresponding to a selected port.
The first chip may be provided with a first time-division transfer circuit and the second chip may be provided with a second time-division transfer circuit so as to transfer the control signal from the first chip to the second chip according to time-division multiplexing, the first and second time-division transfer circuit sharing a first cable between the first chip and the second chip; when data is being transmitted or received, the first control circuit may stop time-division transfer of the control signal by the first time-division transfer circuit and supply a data indication signal indicating that the data is being transmitted or received to the second control circuit using a second cable different from the first cable; and the second control circuit may stop time-division transfer of the control signal by the second time-division transfer circuit when the data indication signal is supplied.
Cables used in the first chip may be smaller than those used in the second chip.
According to the present invention, a higher degree of integration of the first chip using the current microfabrication technology results in a higher degree of integration of many of the circuitry for executing processes on the physical layer. The invention also reduces the number of cables between the link chip and the PHY chip so as to reduce the cost of the interface circuit.
In further accordance with the invention, the number of cables between the link chip and the PHY chip is prevented from increasing even when a plurality of ports are provided on the physical layer.
In still further accordance with the invention, the number of cables is reduced by providing time-division transfer circuits.